There is a known storage device capable of updating data stored therein on the basis of an address and data inputted from the outside (refer to, for example, Patent Document 1). A memory has a first port for reading data and a second port for writing data. A first data holding unit holds the data read from the memory via the first port on the basis of the address inputted from the outside. The address holding unit holds the address inputted from the outside as an address for writing data via the second port. A second data holding unit holds the data inputted from the outside. A data generation unit generates data to be written into the memory via the second port on the basis of the data held in the first and second data holding units.
There is a known semiconductor integrated circuit device that has a data bit storage memory that stores data bits and a code bit storage memory that stores code bits (refer to, for example, Patent Document 2). An error check and correct (ECC) circuit uses the data bit and the code bit and performs error correction on at least one bit in the data bit or the code bit. The data bit storage memory and the code bit storage memory can be independently controlled. When a data write instruction is received, at least one cycle after the data bit is written into the data bit storage memory, the code bit corresponding to the data bit is written into the code bit storage memory.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2011-54221
[Patent Document 2] Japanese Laid-open Patent Publication No. 2005-222618
An error may occur in the data stored in the memory. The ECC circuit can correct an error of one bit in the data. However, if an error further occurs thereafter and an error of two or more bits exists, the ECC circuit cannot correct the error, resulting in a decrease in reliability of the data.